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A Study on Simulation and Characterization of Advanced Si Nano-devices and Applications

차세대 실리콘 나노 소자와 응용에 관한 전산모사 및 특성분석

윤준식 (Yoon, Jun-Sik, 포항공과대학교)

원문보기

  • 주제(키워드) FinFET , Nanowire FET , Applications
  • 발행기관 포항공과대학교 일반대학원
  • 지도교수강봉구
  • 발행년도2016
  • 학위수여년월2016. 2
  • 학위명박사
  • 학과 및 전공일반대학원 창의IT융합공학과
  • 세부전공Smart Devices and Systems
  • 원문페이지149
  • 본문언어영어
  • 저작권포항공과대학교 논문은 저작권에 의해 보호받습니다.
초록 moremore
Bulk FinFETs have been successfully scaled down to 14-nm technology node by adapting rectangular fin structure and air-gap materials at back-end-of-line levels. According to 2013 ITRS roadmap, however, logic transistors in 7 nm technology node would be suffered from severe impacts of parasitic resis...
Bulk FinFETs have been successfully scaled down to 14-nm technology node by adapting rectangular fin structure and air-gap materials at back-end-of-line levels. According to 2013 ITRS roadmap, however, logic transistors in 7 nm technology node would be suffered from severe impacts of parasitic resistances and capacitances on DC/AC performances and variability concerns such as random dopant fluctuation, line edge roughness, and work-function variation. In this study, parasitic components and variability problems of nanoscale FETs have been characterized and analyzed. DC/AC characteristics of Si bulk FinFETs including transistor and middle-of-line levels are precisely investigated using fully-calibrated three-dimensional device simulations for system-on-chip applications. Scaling fin widths down to 5 nm enhances gate-to-channel controllability and improves RC delay, but a critical increase in band-to-band tunneling currents from source to drain can hardly satisfy low-power application limits in the 7-nm node. All lightly-doped extension regions as a solution may decrease band-to-band tunneling currents and total gate capacitances because of better short channel immunity and lower parasitic capacitances, respectively. Using a systematic TCAD-based RC calculation, overlap/underlap lengths in the 7-nm node FinFETs have been optimized. Impacts of random dopant fluctuations on Si nanowire FETs have been investigated in terms of different diameters and extension lengths. Decreasing diameters of nanoscale FETs can cause significant random dopant fluctuations at the extension regions. Si Nanowire FETs with smaller diameter and longer extension length can reduce average values and variations of subthreshold swing and drain-induced barrier lowering, which can improve short channel immunity. Standard deviations of drain currents can decrease greatly as extension length increases due to decreasing the number of arsenic dopants penetrating into channel region. To understand variability origins of drain currents, variations of extension resistance and low-field mobility are evaluated. Both of these two parameters can cause variations of drain currents. Si nanowire FETs with sufficient extension lengths and large cross-sections are preferential to achieve short channel immunity and small variations of DC characteristics. Many researchers have focused on new material-based FETs such as group III-V, carbon nanotube, and 2D materials such as MoS2 and graphene or Si-based FETs with alternative device structure. In case of Si-based FETs, vertical nanowire structure is one of the possible candidates to substitute bulk FinFETs due to higher device density, smaller parasitic elements, and CMOS compatibility. However, top-down fabrication can induce difference of structure and doping concentrations between top-side and bottom-side vertical nanowires causing variation of DC characteristics. Vertical Si nanowire FETs with different diameters and underlap lengths are investigated. Source-side diameters can determine on-state characteristics and drain-induced barrier lowering, whereas drain-side diameters can control band-to-band tunneling currents during off-state conditions. Si nanowire FETs with short drain-side underlap lengths decrease drain-side extension resistance but degrade off-state characteristics due to large bandgap narrowing effects at drain extension regions. Proper device design of vertical Si nanowire FETs have been proposed to improve both drain current on/off ratio and short channel characteristics.
목차 moremore
Contents
ABSTRACT i
Contents v
...
Contents
ABSTRACT i
Contents v
List of Figures viii
List of Tables xv

I. Introduction 1
1.1 General Trend in MOSFET Scaling 1
1.2 Multi-Gate Transistors: Extending Silicon Technology 5
1.3 Advanced Nano Transistors in Logic Technology 9
1.3.1 State-of-the-Art in MOSFETs 9
1.3.2 Simulation Methodology for MOSFETs 11
1.4 Overview of the Thesis 16
REFERENCES 17

II. Characterization of 7-nm node FinFETs Including Transistor and Middle-of-Line Levels 24
2.1 Introduction 24
2.2 Device Structure and Simulation Methodology 26
2.3 Results and Discussion 31
2.3.1 TCAD Calibration to the Experimental Data 31
2.3.2 DC Characteristics of the 7-nm node FinFETs 32
2.3.3 AC Characteristics of the 7-nm node FinFETs 36
2.3.4 RC Delay of the FinFETs 39
2.4 Conclusion 41
REFERENCES 42
III. Statistical Variability Study of Random Dopant Fluctuation on Si Nanowire FETs 45
3.1 Introduction 45
3.2 Simulation Methodology and Parameter Extraction 46
3.3 Results and Discussion 52
3.3.1 Short Channel Characteristics of the Nanowire FETs 52
3.3.2 DC Performance Variation of the Nanowire FETs 54
3.3.3 Statistical Analysis for the Nanowire FETs 56
3.4 Conclusion 61
REFERENCES 62

IV. DC Characterization of Vertical Si Nanowire FETs with Asymmetric Structure and Underlap Lengths 67
4.1 Introduction 67
4.2 Device Structure and Simulation Methodology 68
4.3 Results and Discussion 71
4.3.1 Structural Effects of Junctionless Nanowire FETs 71
4.3.2 Underlap Effects of Junctionless Nanowire FETs 76
4.4 Conclusion 80
REFERENCES 81

V. Conclusion 84

Appendix: Si-based Applications Using Vertical Nanowire Structure 87
A.1 Introduction 87
A.2 Logic Device: Tunneling FET (TFET) 89
A.2.1 Device Structure and Simulation Methodology 89
A.2.2 Structural Effects of Vertical Nanowire TFETs 91
A.3 Photonic Device: Photodetector (PD) 97
A.3.1 Device Structure and Simulation Methodology 97
A.3.2 Structural Effects of Vertical Nanowire PDs 100
A.4 Thermoelectric Devices 107
A.4.1 Simulation Methodology and Parameter Extraction 107
A.4.2 Structural Effects of Vertical Nanowire Thermoelectric Devices 113
A.5 Conclusion 114
REFERENCES 115